FPGA Flow

• Re-configurable Devices
• Architectures of XILINX, ALTERA Devices
• Designing with FPGAs
• FPGA’s and its Design Flows
• Architecture based coding
• Efficient resource utilization
• Constrains based synthesis
• False paths and multi cycle paths
• UCF file creation
• Timing analysis/Floor Planning
• Place and route/RPM
• Back annotation, Gate level simulation, SDF Format
• Writing Scripts
• Hands on experience with industry Standard Tools

 ASIC Flow

• Projects: As a part of course 2 mini projects and 1 major project
• EDA Tools / CAD Flow for IC Design
• Simulation/Synthesis using ASIC libraries
• Clock Tree Synthesis
• False paths / Multi cycle paths / Critical paths
• Design for Testability (DFT)
• Scan Insertion / Types of Scan
• Fault Models
• Logic BIST, Memory BIST, ATGP, Boundary Scan
• Pattern Compression
• Scan Diagnostics
• Layout Design
• Placing and Routing
• LVS/DRC/OPC/Physical verification
• Diagnosis, DFM, Yield Analysis
• SOC Design and Trade-offs
• Future Trends and challenges
• ASIC Case Studies